--  Manchester encoder test bench

library ieee ;
use ieee.std_logic_1164.all ;

entity testbench is 
end testbench;

architecture v1 of testbench is 

	component me
		port (rst : in std_logic ;
		clk16x : in std_logic ;
		wrn : in std_logic ;
		din : in std_logic_vector (7 downto 0);
		tbre : out std_logic ;
		mdo : out std_logic 
		);
	end component ;

	signal rst : std_logic ;
	signal clk : std_logic ;
	signal wr : std_logic ;
	signal din : std_logic_vector (7 downto 0) ;
	signal ready : std_logic ;
	signal mdo : std_logic ;
	
	type test_record is record
		rst : std_logic ;
		wr : std_logic ;
		din : std_logic_vector (7 downto 0) ;
	end record ;
	
	type test_array is array(positive range<>) of test_record ;
	constant test_vectors : test_array := (
	-- rest, wr, din
	('1','0',"00000000"), --0
	('0','0',"10101010"), --0
	('0','1',"10101010"), --0
	('0','0',"10101010"), --1 * 1 bit
	('0','0',"10101010"), --2
	('0','0',"10101010"), --3
	('0','0',"10101010"), --4 
	('0','0',"10101010"), --5
	('0','0',"10101010"), --6
	('0','0',"10101010"), --7 
	('0','0',"10101010"), --8
	('0','0',"10101010"), --9
	('0','0',"10101010"), --10 
	('0','0',"10101010"), --11
	('0','0',"10101010"), --12
	('0','0',"10101010"), --13 
	('0','0',"10101010"), --14
	('0','0',"10101010"), --15
	('0','0',"10101010"), --16
	
	('0','0',"10101010"), --1 * 2 bit
	('0','0',"10101010"), --2
	('0','0',"10101010"), --3
	('0','0',"10101010"), --4 
	('0','0',"10101010"), --5
	('0','0',"10101010"), --6
	('0','0',"10101010"), --7 
	('0','0',"10101010"), --8
	('0','0',"10101010"), --9
	('0','0',"10101010"), --10 
	('0','0',"10101010"), --11
	('0','0',"10101010"), --12
	('0','0',"10101010"), --13 
	('0','0',"10101010"), --14
	('0','0',"10101010"), --15
	('0','0',"10101010"), --16
	
	('0','0',"10101010"), --1 * 3 bit
	('0','0',"10101010"), --2
	('0','0',"10101010"), --3
	('0','0',"10101010"), --4 
	('0','0',"10101010"), --5
	('0','0',"10101010"), --6
	('0','0',"10101010"), --7 
	('0','0',"10101010"), --8
	('0','0',"10101010"), --9
	('0','0',"10101010"), --10 
	('0','0',"10101010"), --11
	('0','0',"10101010"), --12
	('0','0',"10101010"), --13 
	('0','0',"10101010"), --14
	('0','0',"10101010"), --15
	('0','0',"10101010"), --16
	
	('0','0',"10101010"), --1 * 4 bit
	('0','0',"10101010"), --2
	('0','0',"10101010"), --3
	('0','0',"10101010"), --4 
	('0','0',"10101010"), --5
	('0','0',"10101010"), --6
	('0','0',"10101010"), --7 
	('0','0',"10101010"), --8
	('0','0',"10101010"), --9
	('0','0',"10101010"), --10 
	('0','0',"10101010"), --11
	('0','0',"10101010"), --12
	('0','0',"10101010"), --13 
	('0','0',"10101010"), --14
	('0','0',"10101010"), --15
	('0','0',"10101010") --16
	) ;
begin

	uut : me port map (rst,clk,wr,din,ready,mdo) ;	
	process
		variable vector : test_record ;
	begin
	for index in test_vectors'range loop
		vector := test_vectors(index);
		rst <= vector.rst ;
		wr <= vector.wr ;
		din <= vector.din ;
		clk <= '0' ;
		wait for 20 ns ;
		clk <= '1' ;
		wait for 20 ns ;
		clk <= '0' ;
	end loop;
	wait ;
	end process ;
	
end v1;