--    File Name:  md.vhd
--        Model:  Manchester decoder Chip
--
--      Company:  Xilinx

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity md is
	port (rst,clk16x,mdi,rdn : in std_logic ;
			dout : out std_logic_vector (7 downto 0) ;
			data_ready : out std_logic 
	) ;
end md ;

architecture v1 of md is

	signal clk1x_enable : std_logic ;
	signal mdi1 : std_logic;
	signal mdi2 : std_logic;
	signal rsr : std_logic_vector (7 downto 0);
	signal rbr : std_logic_vector (7 downto 0) ;
	signal no_bits_rcvd : unsigned (3 downto 0);
	signal clkdiv : unsigned (3 downto 0);
	signal nrz : std_logic;
	signal clk1x : std_logic;
	signal sample : std_logic;

begin

-- process 1

	process (rst,clk16x)
	begin
		if rst = '1' then
			mdi1 <= '0' ;
			mdi2 <= '0' ;
		elsif clk16x'event and clk16x = '1' then 
			mdi2 <= ? ;
			mdi1 <= ? ;
		end if ;
	end process ;
	
-- process 2

	process (rst,clk16x,mdi1,mdi2,no_bits_rcvd)
	begin
		if rst = '1' then
			clk1x_enable <= '0' ;
		elsif clk16x'event and clk16x = '1' then
			if mdi1 = ? and mdi2 = ? then
				clk1x_enable <= '1' ;
			else if std_logic_vector(no_bits_rcvd) = "?" then
				clk1x_enable <= '0' ;
				end if ;
			end if ;
		end if ;
	end process;	
	
-- process 3

	process (rst,clk16x,clk1x_enable,clkdiv)
	begin
		if rst = '1' then
			clkdiv <= "?" ;
		elsif clk16x'event and clk16x = '1' then
			if clk1x_enable = '1' then
				clkdiv <= ? + ? ;
			end if ;
		end if ;
	end process;

	clk1x <= clkdiv(3) ;
	
-- process 4

	process (rst,clk1x,rbr,nrz)
	begin
		if rst = '1' then
			rsr <= "?" ;
		elsif clk1x'event and clk1x = '1' then
			rsr <= rsr(? downto 0) & ? ;
		end if ;
	end process ;
	
-- process 5

	process (rst,clk1x,no_bits_rcvd)
	begin
		if rst = '1' then
			rbr <= "?" ;
		elsif clk1x'event and clk1x = '1' then
			if std_logic_vector(no_bits_rcvd) = "?" then
				rbr <= rsr ;
			end if ;
		end if ;
	end process ;
	dout <= rbr ;

-- process 6

	process (rst,clk1x,clk1x_enable,no_bits_rcvd)
	begin
		if rst = '1' then 
			no_bits_rcvd <= "?" ;
		elsif clk1x'event and clk1x = '1' then
			if (clk1x_enable = '?') then
				no_bits_rcvd <= "?" ;
			else
				no_bits_rcvd <= ? + "?" ;
			end if ;
		end if ;
	end process ;
	
-- Decodage Manchester data vers NRZ

	sample <=  ? ; 

	process (rst,sample,mdi2,clk16x,no_bits_rcvd)
	begin
		if rst = '1' then
			nrz <= ? ;
		elsif clk16x'event and clk16x = '1' then
			if std_logic_vector(no_bits_rcvd) > "?" and sample = '?' then
				nrz <= ?;
			end if ;
		end if ;
	end process;	
	
-- Generate data_ready status signal

	process (rst,clk1x,clk1x_enable,rdn)
	begin
		if (rst = '1' or rdn = '0') then
			data_ready <= '0' ;
		elsif clk1x'event and clk1x = '1' then
			if (clk1x_enable = '0') then
				data_ready <= '1' ;
			else data_ready <= '0' ;
			end if ;
		end if ;
	end process ;
end v1;