library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity me is
	port (rst,clk16x,wrn : in std_logic ;
			din : in std_logic_vector (7 downto 0) ;
			tbre : out std_logic ;
			mdo   : out std_logic );
end me;

architecture v1 of me is
	signal clk1x : std_logic ;
	signal clk1x_enable : std_logic ;
	signal clkdiv : std_logic_vector (3 downto 0) ;
	signal tsr : std_logic_vector (7 downto 0) ;
	signal tbr : std_logic_vector (7 downto 0) ;
	signal no_bits_sent : std_logic_vector (3 downto 0) ;
	
begin
-- process 1 

	process (rst,clk16x,wrn,no_bits_sent)
	begin
		if rst = '1' or std_logic_vector(no_bits_sent) = "?" then
			clk1x_enable <=  '0' ;
		elsif clk16x'event and clk16x = '1' then
			if (wrn = '?')  then 
				clk1x_enable <= '1' ;
			end if ;
		end if ;
	end process ;

-- process 2

	process (rst,clk16x,clkdiv,clk1x_enable)
	begin
		if rst = '1' then
			clkdiv <= "?" ;
		elsif clk16x'event and clk16x = '1' then
			if clk1x_enable = '1' then
				clkdiv <= ? + ? ;
			end if ;
		end if ;
	end process ;
	clk1x <= clkdiv(3) ;

-- process 3

	process (rst,clk16x,wrn)
	begin
		if rst = '1' then 
			tbr <= "?" ;
		elsif clk16x'event and clk16x = '0' then
			if wrn = '?' then
				tbr <= ? ;
			end if ;
		end if ;
	end process ;
	
-- process 4

	process (rst,clk1x,no_bits_sent,tsr)
	begin
		if rst = '1' then
			tsr <= "00000000" ;
		elsif clk1x'event and clk1x = '1' then
			if std_logic_vector(no_bits_sent) = "0001" then
				tsr <= tbr ;
			elsif std_logic_vector(no_bits_sent) >= "0010" and std_logic_vector(no_bits_sent) <= "1010" then
				tsr <= tsr(? downto 0)  & '?' ;
			end if ;
		end if ;
	end process ;

-- process 5

	process (clk1x,rst,clk1x_enable,no_bits_sent)
	begin 
		if rst = '1' or clk1x_enable = '0' then
			no_bits_sent <= "?" ;
		elsif clk1x'event and clk1x = '1'  then
			if clk1x_enable = '?' then
				no_bits_sent <= ? + "?" ;
			end if  ;
		end if  ;
	end process ;	
	
-- Codage Manchester 
	mdo <= ?;
	
-- Buffer de transmission vide

	process (rst,clk16x,wrn,no_bits_sent)
	begin
		if rst = '1' then
			tbre <= '1' ;
		elsif clk16x'event and clk16x = '1' then
			if (wrn = '1')  then
				tbre <= '0' ;
			elsif (std_logic_vector(no_bits_sent) = "0010") then
				tbre <= '1' ;
			else 
				tbre <= '0' ;
			end if ;
		end if ;
	end process ;
end ;